This invention relates to fault-tolerant computer systems and more particularly to a hardware fault-tolerant real time clock and a method of synchronizing n such clocks (n=3, 5, 7, etc.) so that operation is maintained with a failure of (n-1)/2 of them.
Triple Modular Redundancy (TMR) is a type of fault tolerant system in which three identical machines work synchronously on the same task and their outputs are voted by hardware or software to provide a majority answer as output. Real time clocking for task periods is usually accomplished in software by use of flags. This produces a software overhead liability that reduces the efficiency of the machine. A hardware synchronized clock reduces this software overhead, increasing efficiency. This real time clock should continue to function properly in the face of both transient and hard faults in the system.
Literature references to fault-tolerant clocks deal with the production of high frequency clocks for processor clock applications in which the processors are run tightly synchronized.